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<p>The configuration structure for DPHY.  
 <a href="struct_x_dphy___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:aae49eefd487d5287d24e835c7b17a5e9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#aae49eefd487d5287d24e835c7b17a5e9">DeviceId</a></td></tr>
<tr class="memdesc:aae49eefd487d5287d24e835c7b17a5e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Id.  <a href="#aae49eefd487d5287d24e835c7b17a5e9">More...</a><br/></td></tr>
<tr class="separator:aae49eefd487d5287d24e835c7b17a5e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2494e733c95a9a99495333fd0679222c"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a2494e733c95a9a99495333fd0679222c">BaseAddr</a></td></tr>
<tr class="memdesc:a2494e733c95a9a99495333fd0679222c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Base address of DPHY.  <a href="#a2494e733c95a9a99495333fd0679222c">More...</a><br/></td></tr>
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<tr class="memitem:a357d54e40b4a8ebde78b99d47fa5bb64"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a357d54e40b4a8ebde78b99d47fa5bb64">IsRx</a></td></tr>
<tr class="memdesc:a357d54e40b4a8ebde78b99d47fa5bb64"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX or RX Mode.  <a href="#a357d54e40b4a8ebde78b99d47fa5bb64">More...</a><br/></td></tr>
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<tr class="memitem:a56ad1e1658db486364b0bfc8dd9d9117"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a56ad1e1658db486364b0bfc8dd9d9117">IsRegisterPresent</a></td></tr>
<tr class="memdesc:a56ad1e1658db486364b0bfc8dd9d9117"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is register access allowed.  <a href="#a56ad1e1658db486364b0bfc8dd9d9117">More...</a><br/></td></tr>
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<tr class="memitem:aeae063e9d5b0df42dbad7d68ba4e9d04"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#aeae063e9d5b0df42dbad7d68ba4e9d04">MaxLanesPresent</a></td></tr>
<tr class="memdesc:aeae063e9d5b0df42dbad7d68ba4e9d04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Lanes.  <a href="#aeae063e9d5b0df42dbad7d68ba4e9d04">More...</a><br/></td></tr>
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<tr class="memitem:acba394f3ba96faa365d59e2d71add097"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#acba394f3ba96faa365d59e2d71add097">EscClkPeriod</a></td></tr>
<tr class="memdesc:acba394f3ba96faa365d59e2d71add097"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Clock Peroid.  <a href="#acba394f3ba96faa365d59e2d71add097">More...</a><br/></td></tr>
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<tr class="memitem:a255e8ec1757ac017a2bb60c81a914467"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a255e8ec1757ac017a2bb60c81a914467">EscTimeout</a></td></tr>
<tr class="memdesc:a255e8ec1757ac017a2bb60c81a914467"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Timeout.  <a href="#a255e8ec1757ac017a2bb60c81a914467">More...</a><br/></td></tr>
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<tr class="memitem:ac54787029196f3add5160f3d09f10b24"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#ac54787029196f3add5160f3d09f10b24">HSLineRate</a></td></tr>
<tr class="memdesc:ac54787029196f3add5160f3d09f10b24"><td class="mdescLeft">&#160;</td><td class="mdescRight">High Speed Line Rate.  <a href="#ac54787029196f3add5160f3d09f10b24">More...</a><br/></td></tr>
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<tr class="memitem:a1d0c94e530f0bcd66d703b6572c41a82"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a1d0c94e530f0bcd66d703b6572c41a82">HSTimeOut</a></td></tr>
<tr class="memdesc:a1d0c94e530f0bcd66d703b6572c41a82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max Frame Length.  <a href="#a1d0c94e530f0bcd66d703b6572c41a82">More...</a><br/></td></tr>
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<tr class="memitem:a0ed85384cc546378f890da4108a0b11e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a0ed85384cc546378f890da4108a0b11e">Wakeup</a></td></tr>
<tr class="memdesc:a0ed85384cc546378f890da4108a0b11e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time to exit ULPS mode.  <a href="#a0ed85384cc546378f890da4108a0b11e">More...</a><br/></td></tr>
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<tr class="memitem:a58f6a8702accf8ef4f5affef6efa5565"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dphy___config.html#a58f6a8702accf8ef4f5affef6efa5565">EnableTimeOutRegs</a></td></tr>
<tr class="memdesc:a58f6a8702accf8ef4f5affef6efa5565"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable HS and Esc Timeout Regs.  <a href="#a58f6a8702accf8ef4f5affef6efa5565">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>The configuration structure for DPHY. </p>
<p>This structure passes the hardware building information to the driver </p>
</div><h2 class="groupheader">Field Documentation</h2>
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<p>Base address of DPHY. </p>

<p>Referenced by <a class="el" href="xdphy__example__selftest_8c.html#a238975c776a9aeeea1049a2071f28b7b">DphySelfTestExample()</a>, <a class="el" href="group__dphy.html#gab83aed5a09f62e3a68e5d6cc06bad18d">XDphy_Activate()</a>, <a class="el" href="group__dphy.html#gaea0afc70f0f04baddd321ed49eff751a">XDphy_CfgInitialize()</a>, <a class="el" href="group__dphy.html#ga202a4113c0ace62f6858b7f37dfd0f75">XDphy_ClearDataLane()</a>, <a class="el" href="group__dphy.html#ga455915ec07f1de9a2c68bae01e7bc6f8">XDphy_GetClkLaneStatus()</a>, <a class="el" href="group__dphy.html#ga006589112115f10a2dc19853bae893ce">XDphy_GetDataLaneStatus()</a>, <a class="el" href="group__dphy.html#gaa18b76f92d1ac7c35e0b72d191952273">XDphy_GetDLCalibStatus()</a>, and <a class="el" href="group__dphy.html#ga0da2a930bce29d8c6a2b74d020aa3561">XDphy_GetPacketCount()</a>.</p>

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<p>Device Id. </p>

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<p>Enable HS and Esc Timeout Regs. </p>

<p>Referenced by <a class="el" href="group__dphy.html#ga0d72a217f030e5c452ce1e61c92f1a29">XDphy_Configure()</a>, and <a class="el" href="group__dphy.html#ga08901fa94d34b59883610d1590165919">XDphy_GetInfo()</a>.</p>

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<p>Escape Clock Peroid. </p>

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<p>Escape Timeout. </p>

<p>Referenced by <a class="el" href="group__dphy.html#ga08901fa94d34b59883610d1590165919">XDphy_GetInfo()</a>.</p>

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<p>High Speed Line Rate. </p>

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<p>Max Frame Length. </p>

<p>Referenced by <a class="el" href="group__dphy.html#ga08901fa94d34b59883610d1590165919">XDphy_GetInfo()</a>, and <a class="el" href="group__dphy.html#ga0e170cc371483fc64fd515d1cc301ee4">XDphy_SelfTest()</a>.</p>

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<p>Is register access allowed. </p>

<p>Referenced by <a class="el" href="group__dphy.html#gab83aed5a09f62e3a68e5d6cc06bad18d">XDphy_Activate()</a>, <a class="el" href="group__dphy.html#ga202a4113c0ace62f6858b7f37dfd0f75">XDphy_ClearDataLane()</a>, <a class="el" href="group__dphy.html#ga0d72a217f030e5c452ce1e61c92f1a29">XDphy_Configure()</a>, <a class="el" href="group__dphy.html#gad2110f5c852b9ef0b78a892625051646">XDphy_GetClkLaneMode()</a>, <a class="el" href="group__dphy.html#ga455915ec07f1de9a2c68bae01e7bc6f8">XDphy_GetClkLaneStatus()</a>, <a class="el" href="group__dphy.html#ga0a8e793032f9c635bcbf2abf6a1d9832">XDphy_GetDataLaneMode()</a>, <a class="el" href="group__dphy.html#ga006589112115f10a2dc19853bae893ce">XDphy_GetDataLaneStatus()</a>, <a class="el" href="group__dphy.html#gaa18b76f92d1ac7c35e0b72d191952273">XDphy_GetDLCalibStatus()</a>, <a class="el" href="group__dphy.html#ga08901fa94d34b59883610d1590165919">XDphy_GetInfo()</a>, <a class="el" href="group__dphy.html#ga0da2a930bce29d8c6a2b74d020aa3561">XDphy_GetPacketCount()</a>, <a class="el" href="group__dphy.html#ga4e15b3ffd6c4cfca5eedda2a7c1e9d4d">XDphy_GetRegIntfcPresent()</a>, and <a class="el" href="group__dphy.html#gaef0df18f2a9cdc07df62ba6d63347900">XDphy_Reset()</a>.</p>

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<p>TX or RX Mode. </p>

<p>Referenced by <a class="el" href="group__dphy.html#ga0d72a217f030e5c452ce1e61c92f1a29">XDphy_Configure()</a>, and <a class="el" href="group__dphy.html#ga08901fa94d34b59883610d1590165919">XDphy_GetInfo()</a>.</p>

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<p>Number of Lanes. </p>
<p>Range 1 - 4 </p>

<p>Referenced by <a class="el" href="group__dphy.html#ga0d72a217f030e5c452ce1e61c92f1a29">XDphy_Configure()</a>, and <a class="el" href="group__dphy.html#ga08901fa94d34b59883610d1590165919">XDphy_GetInfo()</a>.</p>

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<p>Time to exit ULPS mode. </p>

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